The present invention relates to multiplexers, and more particularly, the present invention relates to an improved way of implementing multiplexers in integrated circuitry.
Multiplexers are well known elements used commonly in logic circuitry. Because of the prevalent use of multiplexers logic designs, inefficient implementation of multiplexers in hardware constructs will have a pronounced effect in terms of resource usage and execution speed.
Known techniques for implementing a multiplexer typically rely on some aspect of decoding a control signal being sent to the multiplexer in order to determine which of the input signals should be selected as an output. Thus, additional decoding circuitry is used and additional clock cycles are required for the decoding process to complete.
In one known approach, a multiplexer is implemented by using two lookup tables (“LUTs”), the outputs of which are sent into a logic gate that, in turn, outputs the output of the multiplexer. Two or more of such multiplexers may be used as inputs to another multiplexer to implement larger, more complex multiplexer. Such a “cascade” structure is described in Cliff et al. U.S. Pat. No. 5,258,668, issued Nov. 2, 1993. Cliff refers to the benefits attributed to using cascaded connections to couple elements in a programmable logic array using local connections as opposed to a device-wide interconnect. Fewer resources may be used and functions using the larger more complex elements may execute faster.
It would therefore be desirable to provide an improved implementation of a multiplexer to make use of the benefits afforded by a cascading arrangement of LUTs.